1. Field of the Invention
The present invention relates to a semiconductor memory device having self-aligned contacts and a method of fabricating the same, and more particularly, to a semiconductor memory device having contacts for storage electrodes which are simultaneously self-aligned with bit lines and gate electrodes in the structure of a capacitor over bit line (COB) in which a capacitor is formed after the formation of the bit lines, and a method of fabricating the same.
2. Description of the Related Art
As the integration of semiconductor devices increases, the size of a unit cell in a memory cell per unit area is reduced. For example, in the case of a dynamic random access memory (DRAM), the cell size is reduced to less than 1.5 μm2. Reduced cell size can be achieved by decreasing an interval between conductive layers of the cell, and in the case of DRAM, due to high integration, an interval between gate electrodes becomes a minimum feature size according to known design rules.
In addition, as the integration of semiconductor devices increases, the size of the contact holes connecting a lower interconnection layer to an upper interconnection layer, and the interval between contact holes, are reduced, while the aspect ratio of each contact hole is increased. Thus, the formation of contact holes using a photolithographic process in integrated semiconductor devices having a multi-layer interconnection structure is more difficult.
In DRAM, a capacitor over bitline (COB) structure has been developed for improvement of integration. In a COB, the capacitor is formed after the formation of bit lines. In addition, contacts (hereinafter referred to as a “contact for bit line” or a direct contact (DC)) for electrically connecting bit lines to drain regions, and contacts for electrically connecting storage electrodes to source regions (hereinafter referred to as a “contact for storage electrode” or a buried contact (BC)), must be formed. Drain regions are active regions formed around the surface of a semiconductor substrate. Storage electrodes are the lower electrodes of a semiconductor capacitor.
In cases where the contacts for bit lines and the contacts for storage electrodes comprise a conventional small contact type, a short-circuit can occur between the contacts for storage electrodes and contacts for bit lines in the design rule of less than 0.2 μm. Thus, in the COB structure above, in order to smoothly form the contacts for bit lines and the contacts for storage electrodes, pads for bit lines and pads for storage electrodes which are directly connected to the source regions, and the drain regions of the semiconductor substrate, are simultaneously formed. The contacts for bit lines and the contacts for storage electrodes, which are respectively connected to the pads, are then formed.
However, in the design rule of less than 0.15 μm, an interval between the pads for bit lines and the pads for storage electrodes is very narrow. At this size short-circuits can again occur between the contacts for bit lines and the contacts for storage electrodes even when the above methods are implemented.
Therefore, a need exists for a device having self-aligned contacts for preventing short-circuits between contacts for bit lines and contacts for storage electrodes, and a method of producing the same.